The first three days of the week were really frustrating. After a long time, I had to do something just because my boss wanted that. And the only reason he wanted it was because his boss wanted it from him.
An insight into what we do (part of it):
Customer X (its illegal to mention where you get your business from) wants some design on his chip to send some data over a channel and recieve it elsewhere on some other chip. He asks us to design an interface for this. He gives the specifications and we design.
In the age of digital dominance, the scales of IC design are unfavourably tipped against we analog designers. All technologies are optimised for driving either a 1 or a 0 and we analog designers fight with these to drive something like a 0.3 or a 1.3. Morover, we design using simulators, on a computer, which are only as efficient and trustworthy as the models on which they run. The consequence of this, and the digital dominance, is that, WE DONT TRUST OUR OWN DESIGNS. And hence, before we deliver the design to X, we produce many 'test-chips' internally to convince ourselves that what we design on the computer and see as the simulator outcome, is actually seen on silicon. Its akin to lot of net-practice before the cricket match.
I worked on one such module, since Feb 05, for 22 months. The specifications were very aggressive and needed some back-to-the-blackboard approach for a viable solution. And we did come up with an innovative idea for the same. The patent that I mentioned sometime back was for this idea. We needed 4 test-chips in this span to convince ourselves that the design would actually work. And when we were, in early 07, the chip was cancelled and so were all the modules that went into it. Apart from some knowledge and experience building and a patent, all other effort went down the drain.
The final testchip came back from the fab last month. The ending was painful but I have 'moved on' now. 6 months have passed and now we have a much better solution, smaller in area (the previous dsign was in 65nanometer technology as aginast 45nanometer now) with lower wattage for those specifications. The previous design can be dumped for good.
But no! My boss's boss wanted to understand if that previous design could be confidently signed off as a stable design. Off I was sent to the lab to 'characterize' its performance. And 3 days I lost in proving this. But the worst part (I havent told this to my boss) is that I have the Silicon results but I seem to have lost the data from the simulator to compare with. There is so much data that I have no clue which one is the latest. C'mon! Its been over 6 months now. How am I supposed to remember! All this is so inconsequential that half my mind is coaxing me to 'cook-up' data from the simulator and tell the world that all is fine. I might do that soon.
I was frustrated for I worked on a testchip that has a module based on an idea that has long been dropped, for a project that no longer exists, in a process node that has become obsolete.
Very similar to this, aint it?
Dilbert: As usual I worked until midnight last night, mom.
Dilmom: At least you made some extra money.
Dilbert: I don't get paid for overtime.
Dilmom: Well, at least it was important work.
Dilbert: Not really. My boss made me change my "PowerPoint" slides, but the changes made them worse.
Dilmom: Well, at least you're prepared for your meeting.
Dilbert: It was cancelled. But that's okay because the project isn't funded anyway.
Dilmom: So ... you worked for free to worsen a presentation for a meeting that won't happen for a project that doesn't exist.
Dilbert: Yup.
An insight into what we do (part of it):
Customer X (its illegal to mention where you get your business from) wants some design on his chip to send some data over a channel and recieve it elsewhere on some other chip. He asks us to design an interface for this. He gives the specifications and we design.
In the age of digital dominance, the scales of IC design are unfavourably tipped against we analog designers. All technologies are optimised for driving either a 1 or a 0 and we analog designers fight with these to drive something like a 0.3 or a 1.3. Morover, we design using simulators, on a computer, which are only as efficient and trustworthy as the models on which they run. The consequence of this, and the digital dominance, is that, WE DONT TRUST OUR OWN DESIGNS. And hence, before we deliver the design to X, we produce many 'test-chips' internally to convince ourselves that what we design on the computer and see as the simulator outcome, is actually seen on silicon. Its akin to lot of net-practice before the cricket match.
I worked on one such module, since Feb 05, for 22 months. The specifications were very aggressive and needed some back-to-the-blackboard approach for a viable solution. And we did come up with an innovative idea for the same. The patent that I mentioned sometime back was for this idea. We needed 4 test-chips in this span to convince ourselves that the design would actually work. And when we were, in early 07, the chip was cancelled and so were all the modules that went into it. Apart from some knowledge and experience building and a patent, all other effort went down the drain.
The final testchip came back from the fab last month. The ending was painful but I have 'moved on' now. 6 months have passed and now we have a much better solution, smaller in area (the previous dsign was in 65nanometer technology as aginast 45nanometer now) with lower wattage for those specifications. The previous design can be dumped for good.
But no! My boss's boss wanted to understand if that previous design could be confidently signed off as a stable design. Off I was sent to the lab to 'characterize' its performance. And 3 days I lost in proving this. But the worst part (I havent told this to my boss) is that I have the Silicon results but I seem to have lost the data from the simulator to compare with. There is so much data that I have no clue which one is the latest. C'mon! Its been over 6 months now. How am I supposed to remember! All this is so inconsequential that half my mind is coaxing me to 'cook-up' data from the simulator and tell the world that all is fine. I might do that soon.
I was frustrated for I worked on a testchip that has a module based on an idea that has long been dropped, for a project that no longer exists, in a process node that has become obsolete.
Very similar to this, aint it?
Dilbert: As usual I worked until midnight last night, mom.
Dilmom: At least you made some extra money.
Dilbert: I don't get paid for overtime.
Dilmom: Well, at least it was important work.
Dilbert: Not really. My boss made me change my "PowerPoint" slides, but the changes made them worse.
Dilmom: Well, at least you're prepared for your meeting.
Dilbert: It was cancelled. But that's okay because the project isn't funded anyway.
Dilmom: So ... you worked for free to worsen a presentation for a meeting that won't happen for a project that doesn't exist.
Dilbert: Yup.
6 comments:
awesome anectode.. and a gud insight into trical techie kinda work!!
similar stuff happens in research too.. at times.. we do stuff that has no relevance to our research only coz it improves some research proposal that the advisor is coming up with! and even worse.. 6 months down the line ... after its even more obsolete.. its assumed that we have all code and simulation data ready for a new masters student to work on his/her thesis :D
:))
Dilbert does sum up situations pithily doesnt he?
dilbert comes pretty close to our lives :) interesting post... and i didnt know that u had a patent.. congrats!
Its ok buddy....
C'est la vie...
Don't you think you should be a bit mroe discreet in your posts....?
hahaha... How true :)
That's why people prefer management studies rather than coding and debuggin ;-)
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